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  1. 30 Μαΐ 2014 · By combining silicon thickness measurement, wet etch, and cleaning in a single-wafer process system, this platform provides a low cost-of-ownership solution for TSV reveal. The process uses a wet etch chemistry with a fast etch rate and high selectivity, in a single-wafer process tool.

  2. 5 Ιουν 2014 · The whole TSV reveal process begins with grinding the device wafer, which has been temporarily bonded to a wafer carrier, to 5-10µm above the TSV. The goal is to use etch processes to remove the remaining silicon to achieve a 50µm thinned wafer with exposed TSV Cu contacts.

  3. We are developing etch processes for optimized via profiles such as tapered. filling of large TSVs. Wafer thinning. With coarse and fine grinding processes Si, glass or ceramic wafers could be thinned to thicknesses as low as 50 μm.

  4. In 3D IC packaging, through silicon via (TSV) technology is being considered as a promising technology, enabling massive and short interconnections between stacked chips, increasing performance and data bandwidth, and reducing signal delay and the power consumption.

  5. 20 Ιουν 2014 · Performed on SSEC’s WaferEtch™ platform, which features integrated metrology for performing thickness measurement and end point detection, this wet etch TSV reveal process replaces four tools required for dry etch process including: CMP, plasma etch, clean, and silicon thickness measurement.

  6. 31 Ιαν 2012 · We show the results of TSV reveal using both a wet and dry etch. A set of measurements is performed on the TSV wafers and the bonded stack to select etch parameters to achieve the desired TSV reveal height after the etch.

  7. 27 Μαΐ 2014 · By combining silicon thickness measurement, wet etch, and cleaning in a single-wafer process system, this platform provides a low cost-of-ownership solution for TSV reveal. The process uses a wet etch chemistry with a fast etch rate and high selectivity, in a single-wafer process tool.

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