Αποτελέσματα Αναζήτησης
31 Ιαν 2012 · We show the results of TSV reveal using both a wet and dry etch. A set of measurements is performed on the TSV wafers and the bonded stack to select etch parameters to achieve the desired TSV reveal height after the etch.
- Optimization and challenges of backside via flatness reveal process
In this paper, we use backside via flatness reveal process...
- Si dry etching for TSV formation and backside reveal
In 3D IC packaging, through silicon via (TSV) technology is...
- Optimization and challenges of backside via flatness reveal process
16 Ιουλ 2015 · In this paper, we use backside via flatness reveal process (named as BFR). The process steps include: carrier bond, wafer grinding to via surface exposed, silicon and via surface polishing by CMP, wet etching to reveal Cu nails, etching post-cleaning, passivation deposition with PECVD, and 2nd via reveal by CMP.
In 3D IC packaging, through silicon via (TSV) technology is being considered as a promising technology, enabling massive and short interconnections between stacked chips, increasing performance and data bandwidth, and reducing signal delay and the power consumption.
1 Ιαν 2012 · By combining silicon thickness measurement, wet etch, and cleaning in a single-wafer process system, this platform provides a low cost-of-ownership solution for TSV reveal.
1 Μαΐ 2013 · Based on the full wet etching mechanism of silicon, we designed experiments to obtain the satisfied etching rate, selectivity and etching profile with optimized parameters.
Via Reveal Processing Through silicon vias (TSVs) are being implemented in place of traditional scaling for increasing device performance and reducing form factor. SPTS plasma etch and deposition are used for initially creating and lining these interconnect vias. In addition, SPTS processes can also be used for post-TSV steps,
27 Μαΐ 2014 · This paper presents a wet process as a simple and cost-effective alternative to the polish/plasma etch TSV reveal process. By combining silicon thickness measurement, wet etch, and cleaning in a single-wafer process system, this platform provides a low cost-of-ownership solution for TSV reveal.
